Why does pipelining improve performance

Same here, with a pipeline it doesnt mean you can fetch, decode, and execute all three steps at the clock rate for the processor. Like the factory it is more of an average thing. If you can feed each of the stages in the pipeline at the processor clock rate then it will complete one instruction per clock if designed to do that. I thought it was used when there are branches in the code, and the logic predicts which branch will be taken, and preloads the instructions for that branch into a cache.

If the prediction proves to be false, then it needs to throw away those instructions and load the alternate, resulting in a loss. But I believe there are patterns in code that make the prediction true more often than not, especially with modern compilers that repeat patterns over and over. I'm not up on the actual implementation, but I don't really think that additional hardware is necessarily required, although it is useful for optimum speed.

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What is pipe-lining? Improve this question. Oliver Charlesworth k 29 29 gold badges silver badges bronze badges. Sandeep Sandeep This is exactly what Henry Ford did a years ago. You don't have to wait for one car or instruction to be completed before starting to work on the next one. I'm surprised that no one has mentioned it but pipelining increases throughput which in turn achieves better IPC and hence performance.

Add a comment. Active Oldest Votes. Here's one way of breaking it down for example only, this doesn't necessarily correspond to real hardware : Parse out the binary-encoded instruction to find out which instruction it is. Once you recognize that it is an addi instruction, parse out the source and destination registers and the literal integer to add. Read the appropriate register, and compute the sum of its value and the immediate integer. Write the result into the named result register. Pipelining takes advantage of this observation: If the processor needs to execute two addi instructions in a row, then it can: Identify the first one Parse the first one, and identify the second one with circuits that would otherwise be idle Add the first one, and parse the second Write out the first one, and add the second Write out the second one So now, even though each instruction takes 4 processing rounds, the processor has finished two instructions in just 5 rounds total.

Improve this answer. One more thing. So the units itself can be more compact than the whole block would be. This enables higher clock speeds because the hardware propagation delays are reduced electrons need time to travel through the silicon and switch the transistors.

Oliver Charlesworth Oliver Charlesworth k 29 29 gold badges silver badges bronze badges. I would like to get more clarity as to how it all happens? Any useful links can be of real help. Rather than try to cram a year-long university course into this text box, I'll point you at a textbook that explains this whole subject in clear detail: Hennessy, John L. In this example, the result of the load instruction is needed as a source operand in the subsequent ad.

The notion of load-use latency and load-use delay is interpreted in the same way as define-use latency and define-use delay. The latency of an instruction being executed in parallel is determined by the execute phase of the pipeline.

Two cycles are needed for the instruction fetch, decode and issue phase. The subsequent execution phase takes three cycles. At the end of this phase, the result of the operation is forwarded bypassed to any requesting unit in the processor.

Finally, in the completion phase, the result is written back into the architectural register file. How does pipelining improve performance in computer architecture? Computer Architecture Computer Science Network. To alleviate this problem, branch prediction can be used, but this too can have a negative effect if the branches are predicted wrongly.

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